Heterogeneous Integration & Technology 2017

Heterogeneous integration of packaging has been embrace as the next revolutionary innovation to meet the quest of size, cost and performance for packaging. The technologies are seen as another disruptive technologies to bring devices into a package by integrating the various Multi-chip module (MCM), 3D packaging, Through Silicon Via (TSV) and Fan-out wafer level packaging (Fo-WLP) technologies into a package for applications.


This 2 days workshop reviews the needs of the packaging solution to meet the demand for digitalization through the Internet-of-things for mobile solutions in car, home and urbanization. The course provides an overview of the fabrication process of IC carriers of leadframe, ceramics, substrate and flex and how they have to evolve to meet the heterogeneous integration. With these foundations, various stacking and integration technologies through wirebonding and 3D interconnect for first level and 2nd level packaging will be shared. Process innovation of TSV and its challenges will also be shared for integration.

Fo-WLP as a mean to fill the gap of heterogeneous integration will also be discussed. This includes integration through Option for die first and die last for FO WLP. Assembly challenges of FO-WLP and its future direction to meet integration will also be shared. With the dynamics landscape, the workshop will lso review the design rule of various substrates and how they have evolved to meet the heterogeneous integration for growth with wirebonding and flip chip technologies.

The course looks into the R&D development as well as the dynamics changes of heterogeneous integration technologies in the Semiconductor packaging arena. This workshop curates the technologies development to date and provides the necessary information for professionals in the manufacturing and R&D environment to perform their tasks.


i. Why heterogeneous Integration for Packaging?
ii. Overview of IC carriers
iii. 3D and TSV for Heterogeneous Integrationiv. FO-WLP and their R&D progresses for Heterogeneous Integration
v. The evolution of substrate material solutions to compete against FO-WLP for Heterogeneous Integration

Who Should Register

  • Directors and Managers
  • Research and Design Engineers
  • Product Engineers
  • Equipment and Process Engineers
  • Quality & Reliability Engineers; and
  • Senior Technicians and Operators

Course Fee*

SEMI Members

Student Rate**

SGD 500 / RM 1,500 per pax
SGD 630 / RM 1,900 per pax

SGD 83 / RM 250 per pax

*Fee is inclusive of lunch and coffee/tea breaks for both days.

**Valid Student Pass must be produced as proof.

Please complete the delegate registration form.

Applicable to Malaysia companies only:

Course fee will be debited from Human Resource Development Fund (HRDF) and employers will be given 100% finanical assistance (subjects to terms and conditions). 

REGISTER EARLY and double your chance of winning the latest SAMSUNG GALAXY TAB ! Seats are limited and based on first-come-first-serve basis !

Click here to DOWNLOAD seminar flyer

Sponsorship contact:

Shannen Koh (Ms), Email : [email protected], DID : +65.6391.9511

Registration contact:

Linda Tan (Ms), Email : [email protected], DID : +65.6391.9519

Organized by:

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Supporting Partner :


Event Information

14 Nov 2017 - 15 Nov 2017
08:30 AM - 05:00 PM
MIDA HQ (KL Sentral), Kuala Lumpur, Malaysia
Last Updated : Thursday 21st February 2019